1. Field of the Invention
The present invention relates to a circuit for controlling a rotational velocity of a disk, and more specifically to a disk rotational velocity controlling circuit for controlling a rotational velocity of a disk such as a CD (compact disk), of a CLV (constant linear velocity) type.
2. Description of Related Art
Prior art disk rotational velocity controlling circuits of this type have been used to constitute a velocity controlling circuit in a signal reproducing apparatus for a recording medium such as a CD, in which information is recorded in a PCM (pulse code modulation) format, as a reproducing velocity controlling device disclosed in Japanese Patent Application Pre-examination Publication No. JP-A-61-126665, (an English abstract of JP-A-61-126665 is available from the Japanese Patent Office, and the content of the English abstract of JP-A61-126665 is incorporated by reference in its entirety into this application) (Prior Art Reference 1) or in Japanese Patent Application Pre-examination Publication No. JP-A-58-056258 or U.S. Pat. No. 4,532,561 claiming Conventional Priorities based on JP-A-58-056258 and three other Japanese patent applications, (the content of which is incorporated by reference in its entirety into this application) (Prior Art Reference 2).
Referring to FIG. 1, there is shown a block diagram of the first prior art disk rotational velocity controlling circuit. This shown first prior art disk rotational velocity controlling circuit comprises a disk 10 such as a CD in which digital information is recorded in an EFM (eight-to-fourteen Modulation) format and in the CLV type, a signal reproduction circuit 101 receiving an analog signal AR read out from the disk 10 by a pickup device (not shown), for converting the analog signal into a digital signal to generate an EFM signal E, a clock generator 8 for generating a clock CK, an edge detection circuit 102 receiving the EFM signal E and the clock CK for detecting an edge which is a level transition of the EFM signal, in synchronism with the clock CK, and for generating an edge detection signal EG, and a pattern width detection circuit 104 receiving the edge detection signal EG and the clock CK for calculating the width of the synchronous pattern from the edge detection signal EG and generating a disk rotation control signal CR.
Now, an operation of the prior art disk rotational velocity controlling circuit will be described with reference to FIG. 1. In order to elevate a recording density, the digital disk typified by the CD adopts the CLV type in which the linear velocity is maintained at constant regardless of which of an inner periphery and an outer periphery the signal is recorded in. Therefore, the rotational velocity of the disk must be changed in accordance with a reading position in a radial direction of the disk. For this purpose, a control is carried out to calculate a current linear velocity from a synchronous signal pulse included in the signal AR read out from the disk 10, and to maintain the linear velocity at a predetermined constant velocity.
In a CD modulation system, the frequency of the clock CK for giving the reference for the detection of the velocity is 4.3218 MHz, and therefore, a clock period T=1/4.3218 MHz. Information is recorded by patterns having the width (or duration) of three times to eleven times of the clock period T (namely, 3T to 11T). This information recording is performed in units of one frame which is composed of 588 bits, namely, 588T, and an information recording region or section is so configured that two or more maximum pattern widths of 11T never continue. On the other hand, a synchronous signal pattern for a frame synchronism (called a "synchronous pattern" hereinafter) is defined by a high level having a duration (namely, width) of 11T and a succeeding low level having a duration (namely, width) of 11T or a low level having a duration of 11T and a succeeding high level having a duration of 11T. Namely, the synchronous pattern is defined as two continuous maximum pattern widths (or durations), and is recorded at every 588T. Thus, it is possible to adjust the rotational velocity of the disk by detecting the two continuous maximum pattern widths as the synchronous pattern, and calculating a difference between the detected maximum pattern width and a maximum pattern width 11T corresponding to a normal rotation linear velocity. For example, if the detected maximum pattern width is larger than 11T, namely, if it is discriminated that the disk rotation linear velocity is slower than the normal rotation linear velocity, the control signal CR is generated to accelerate the disk rotational velocity. On the other hand, if the detected maximum pattern width is shorter than 11T. namely, if it is discriminated that the disk rotation linear velocity is faster than the normal rotation linear velocity, the control signal CR is generated to decelerate the disk rotational velocity. If the detected maximum pattern width is equal to 11T, namely, if it is discriminated that the disk rotation linear velocity is at the normal rotation linear velocity, the control signal CR is generated to maintain the disk rotational velocity as it is.
The signal reproduction circuit 101 converts the read-out signal AR into a digital signal to generate and output the EFM signal E to the edge detection circuit 102. The clock generator 8 generates the clock CK having the period T, and supplies the clock CK to the edge detection circuit 102 and the pattern width detection circuit 104. The edge detection circuit 102 detects the edge which is the level transition of the EFM signal E, in synchronism with the clock CK received, and generates and outputs the edge detection signal EG to the pattern width detection circuit 104. The pattern width detection circuit 104 responds to the edge detection signal EG, to detect the pattern width and to generate the disk rotation control signal CR for the disk acceleration, the disk deceleration or the disk velocity maintaining, on the basis of the difference between the detected pattern width and 11T.
Referring to FIG. 2, there is shown a circuit diagram of the edge detection circuit 102. This edge detection circuit 102 includes a buffer amplifier A201 receiving and amplifying the EFM signal E to generate an amplified signal EA, cascaded inverters I201 and I202 receiving the clock CK to generate a delayed clock CKD having a predetermined delay from the clock CK, a D-type flipflop F201 receiving the signal EA and controlled by the delayed clock CKD to output a signal ED1 which is delayed from the signal EA by one clock, another D-type flipflop F202 receiving the signal ED1 and controlled by the delayed clock CKD to output a signal ED2 which is delayed from the signal ED1 by one clock, and an exclusive OR gate EX201 receiving the signals ED1 and ED2 to generates an exclusive OR signal between the signals ED1 and ED2, as the edge detection signal.
Now, an operation of this edge detection circuit 102 will be described. If the EFM signal E is supplied to the buffer amplifier A201, the buffer amplifier A201 outputs the amplified EFM signal EA. The D-type flipflop F201 outputs, as the signal ED1, the signal EA after delaying the same by one clock and in synchronism with the delayed clock CKD. This signal ED1 is supplied to the D-type flipflop F202 and the exclusive OR gate EX201. The D-type flipflop F202 outputs, as the signal ED2, the signal ED1 after delaying the same by one clock and in synchronism with the delayed clock CKD. This signal ED2 is supplied to the exclusive OR gate EX201. The exclusive OR gate EX201 executes the exclusive OR logical operation between the signals ED1 and ED2, to detect the edge where the level of the EFM signal changes, and to generate the edge detection signal EG.
Referring to FIG. 3, there is shown a circuit diagram of the pattern width detection circuit 104. The shown pattern width detection circuit 104 includes a pattern width detector 41 receiving the edge detection signal EG and the clock CK to measure a time interval between each pair of continuous edge detection signals EG, by use of the clock CK, so as to determine the pattern width of the EFM signal E, and to generate a pattern width signal W, and a decoder 42 receiving the pattern width signal W to decode a difference between the received pattern width signal W and a predetermined pattern width, and to generate a disk deceleration signal RW or a disk acceleration signal FF.
Now, an operation of the pattern width detection circuit 104 will be described. The pattern width detector 41 measures the time interval between each pair of continuous edge detection signals EG, by counting the clock CK, and outputs the measured value W of the time interval to the decoder 42. Here, for calculation of the linear velocity of the disk rotation, a clock having the period T/N (where N is an integer) can be used in place of the clock CK. The decoder 42 calculates, from the measured value W, the pattern width corresponding to the measured value W, and also calculates a difference between the calculated pattern width and the predetermined pattern width which corresponds to a predetermined normal rotation linear velocity. If the difference is positive, since the rotational velocity is too high, the decoder 42 generates the disk deceleration signal RW. Alternatively, if the difference is negative, since the rotational velocity is too low, the decoder 42 generates the disk acceleration signal FF.
Here, consider a disk rotation starting time or a draw-in operation for example at the time of a track jump in which the position of a pickup is moved at random. If only the maximum pattern width of 11T in the read-out signal from the disk is measured as mentioned above, the precision for drawing to the predetermined rotation linear velocity becomes 1/11. In other words, the change rate of the disk linear velocity becomes 9.09%. This becomes a cause for lowering the access speed and the draw-in time in for example the track jump.
In order to improve the above mentioned disadvantage, there is a method for increasing the frequency of the disk rotation linear velocity detecting clock to N times, as mentioned above. In this case, however, an operation margin in the rotational velocity detection circuit becomes small for the reason explained hereinafter, and therefore, it becomes difficult to be applied to a four-time speed reproduction or an eight-time speed reproduction which are now widely used in CD-ROM (compact-disk read-only-memory) reproducing devices which are now being spread as a recording medium for a computer, and to a reproduction speed which is expected to be further elevated in future.
At present, the conventional reference clock frequency for CD is 4.3218 MHz (clock period T=1/4.3218 MHz) as mentioned hereinbefore. If N=2 is realized in order to double the detection precision, the detection clock frequency becomes 8.6436 MHz. In this device, if the reproduction speed is made to eight times, a required detection clock frequency becomes 69.1488 MHz, and therefore, a circuit design becomes difficult.
Referring to FIG. 4, there is shown a block diagram of a second prior art disk rotational velocity controlling circuit, which is JP-A-59-172180, (an English abstract of JP-A-59-172180 is available from the Japanese Patent Office, and the content of the English abstract of JP-A-59-172180 is incorporated by reference in its entirety into this application) (Prior Art Reference 3). As shown in FIG. 4, the second prior art disk rotational velocity controlling circuit is different from the first prior art disk rotational velocity controlling circuit, mainly in that, in place of the pattern width detection circuit 104, there is provided a shift register 206 receiving the edge detection signal EG and performing a shift operation in response to a clock CK for the velocity detection.
The number of stages in this shift register 206 is set to be larger than the number of reference clocks CK which should be generated in a synchronous signal generating period when the linear velocity of the recording track of the disk is normal, and the linear velocity is detected in accordance with the output content of the respective stages of the shift register 206. In this example, since the clock CK for the velocity detection is made to T/2, and since the pattern width of the synchronous signal to be detected is 11T.times.2=22T, the number of stages required in this shift register 206 at the normal velocity is 44 (=22T.div.T/2). Therefore, by adding three stages as a detection toleration in the case that the disk rotation linear velocity is slower than the normal velocity, this shift register 206 is set to have 47 stages. In FIG. 4, 23 stages at a right side of a central position "X" in the shift register 206 are numbered "1" to "23" in order towards a right end stage, and 24 stages at a left side are numbered "-1" to "--24" in order towards a left end stage.
The edge detection signal EG has the pattern width of T/2. In the case of the normal velocity, the synchronous signal pattern width is 22T, and in the shift register 206, the stages having a non-inverted output of "1" include the stages "22", "-1" and "-23", and the other stages have an non-inverted output of "0". If the linear velocity elevates so that the synchronous signal pattern width becomes 21T, the shift register 206 changes to the effect that the stages "21", "-1" and "-22" have an non-inverted output of "1" and the other stages have an non-inverted output of "0". To the contrary, if the linear velocity lowers so that the synchronous signal pattern width becomes 23T, the shift register 206 changes to the effect that the stages "23", "-1" and "-24" have an non-inverted output of "1" and the other stages have an non-inverted output of "0".
The output content of the respective stages of the shift register 206 is detected by a combinational circuit composed of a combination of known AND circuits and OR circuits, and whether the linear velocity is slower or faster than the normal velocity, is detected on the basis of the result of the detection.
The second prior art disk rotational velocity controlling circuit as mentioned above, has a high detection precision, but becomes large in circuit scale. Namely, the synchronous signal pattern width of the read-out signal from the EFM recording disk is 22T (=11T.times.2) as mentioned above, and the minimum required stage number of the shift register storing the edge pattern in synchronism with the reference clock (T) becomes 22+.alpha.. Therefore, when the velocity detecting clock signal frequency is 2N as in this example, the minimum required stage number becomes 44+.alpha.. In addition, in order to detect all the contents of the stages of the shift register, the velocity detecting logic circuit becomes large in circuit scale.
In brief, since the first prior art disk rotational velocity controlling circuit as mentioned above uses only 11T which is a maximum pattern width value of the signal read out from the disk, the first prior art disk rotational velocity controlling circuit is disadvantageous in that the velocity detecting precision is low, and the access speed in the track jump or the like becomes low and the draw-in time becomes long.
In order to improve the just above mentioned problem, there is considered the method for elevating the frequency of the disk rotation linear velocity detecting clock to integer times of the reference clock frequency. However, this method reduces the operation margin of the disk rotational velocity detecting circuit. Furthermore, it is difficult to apply this method to the four-time speed reproduction or the eight-time speed reproduction which are now widely used in CD-ROM (compact-disk read-only-memory) reproducing which are now being spread as a recording medium for a compute, and to a reproduction speed which is expected to be further elevated in future.
On the other hand, since the second prior art disk rotational velocity controlling circuit as mentioned above is constructed to store the edge pattern in synchronism with the rotation linear velocity detecting clock, which is adapted to the synchronous signal pattern width 22T of the read-out signal from the EFM recording disk, the minimum required stage number of the shift register is large. In addition, the scale of the velocity detecting logic circuit for detecting all the contents of the stages of the shift register, becomes large, and therefore, the circuit scale becomes large.